module alu (
  input clk,
  input rst,
  input [1:0] alu_op, // 00: Add, 01: Subtract, 10: Multiply (unsigned)
  input signed [7:0] a,
  input signed [7:0] b,
  output reg signed [15:0] result,
  output reg overflow,
  output reg zero_flag
);

  always @(posedge clk) begin
    if (rst) begin
      result <= 0;
      overflow <= 0;
      zero_flag <= 0;
    end else begin
      case (alu_op)
        2'b00: begin // Add
          result <= a + b;
          overflow <= (a[7] == b[7]) && (result[7] != a[7]); // Signed overflow
          zero_flag <= (result == 0);
        end
        2'b01: begin // Subtract
          result <= a - b;
          overflow <= (a[7] != b[7]) && (result[7] != a[7]); // Signed overflow
          zero_flag <= (result == 0);
        end
        2'b10: begin // Multiply (unsigned)
          result <= a * b; // Unsigned multiplication
          overflow <= (result[15] != 0); // Overflow if result doesn't fit
          zero_flag <= (result == 0);
        end
        default: begin
          result <= 0; // Default case (optional)
          overflow <= 0;
          zero_flag <= 0;
        end
      endcase
    end
  end

endmodule


// Testbench (example)
module alu_tb;
  reg clk;
  reg rst;
  reg [1:0] alu_op;
  reg signed [7:0] a;
  reg signed [7:0] b;
  wire signed [15:0] result;
  wire overflow;
  wire zero_flag;

  alu dut (
    .clk(clk),
    .rst(rst),
    .alu_op(alu_op),
    .a(a),
    .b(b),
    .result(result),
    .overflow(overflow),
    .zero_flag(zero_flag)
  );

  initial begin
    clk = 0;
    forever #5 clk = ~clk; // 10ns clock period
  end

  initial begin
    rst = 1;
    alu_op = 2'b00; // Add initially
    a = 0;
    b = 0;
    #10 rst = 0;

    // Test cases (examples)
    a = 5; b = 3; #10;  // Add
    alu_op = 2'b01; a = 10; b = 5; #10; // Subtract
    alu_op = 2'b10; a = 4; b = 5; #10; // Multiply

    $finish;
  end

endmodule